# Five Ways NVIDIA Co-Design Maximizes AI Factory Memory Efficiency NVIDIA leverages hardware and software co-design to boost throughput per megawatt for agentic AI. - **Source:** [Nvidia Developer Blog](https://developer.nvidia.com/blog) - **Published:** 2026-11-05 - **Topic:** [technology](https://brifing.si/c/technology) - **Original article:** - **On Brifing:** https://brifing.si/s/0b0b4771-1b21-440e-910b-2533b77800ce ## Maximizing AI Memory Value In modern AI factories, high bandwidth memory is the most contested resource. NVIDIA focuses on maximizing the useful work delivered by every byte rather than just increasing total capacity. By co-designing GPU architecture, interconnects, and software, they aim to eliminate redundant weight copies and idle cache, significantly boosting overall system throughput. ## NVFP4 Precision Format NVFP4 introduces a 4-bit format with dual-level scaling to reduce model footprints. It provides a 3.5x reduction compared to FP16 and 1.8x versus FP8 while maintaining high accuracy. This format frees up critical HBM capacity, allowing for larger batches and higher concurrency, which are essential for demanding agentic inference workloads. ## Wide Expert Parallelism Wide expert parallelism in TensorRT-LLM distributes experts across eight or more GPUs to optimize weight usage. By spreading the load, each GPU holds fewer expert weights, increasing arithmetic intensity through weight reuse. This strategy prevents GPUs from spending excessive memory on redundant weight copies, ensuring bytes remain active and productive. ## Dynamo Distributed Serving NVIDIA Dynamo treats the KV cache as a fleet-wide resource rather than a per-GPU side effect. It utilizes KV-aware routing and disaggregated serving to manage cache across the system. This approach prevents unnecessary recomputation by ensuring that prefixes are available where needed, effectively closing the gap between memory location and usage. ## NIXL Storage Integration NIXL connects the KV cache offloading path to external storage systems, enabling fast retrieval. Validation tests with VAST Data and WEKA showed aggregate read throughput reaching 270 GB/s across eight H100 GPUs. This capability allows systems to support cache capacity far beyond the physical limits of local GPU HBM memory. ## Vera CPU Performance The NVIDIA Vera CPU features 88 Olympus cores and 1.5 TB of LPDDR5X memory. It delivers 1.8x faster single-threaded performance and connects to Rubin GPUs at 1.8 TB/s via NVLink-C2C. This architecture allows for staging idle KV cache during tool calls, preventing the need for expensive recomputation when the agent resumes. ## Optimizing Idle Sessions During tool calls or database queries, session KV cache often sits idle in HBM. Vera CPU memory acts as a warm tier, holding this cache during gaps. This strategy keeps HBM dedicated to active token generation, ensuring that paused sessions do not force the system to perform a full prefill upon restart. ## CMX Context Memory NVIDIA CMX adds a pod-level G3.5 storage tier built on BlueField-4 STX and Spectrum-X. This tier is specifically optimized for KV cache, allowing for reuse across different nodes. By pooling context storage, CMX reduces duplication and stranded capacity, effectively extending the memory available for long-context inference and multi-agent workflows. ## Pod-Level Cache Reuse The CMX design enables prefixes computed on one node to be reused by compatible model instances across the pod. This reduces inference stalls and lowers power overhead by avoiding redundant computations. Consequently, CMX delivers up to 5x higher tokens per second and improved power efficiency compared to traditional enterprise storage solutions. ## Stacking Efficiency Levers These five levers work as a unified memory system rather than independent components. A 4-bit KV block saves space across HBM, Vera memory, and CMX storage simultaneously. This holistic co-design approach ensures that gains stack, allowing the Vera Rubin NVL72 to deliver massive throughput improvements from the same 288 GB per GPU. ## Future of AI Throughput The Vera Rubin NVL72 achieves up to 30x the throughput per megawatt compared to the GB300 NVL72. This evolution highlights a shift toward measuring AI factory performance by useful tokens produced per byte. As agentic workloads grow, this co-design philosophy becomes essential for maintaining efficiency in increasingly complex, large-scale computing environments. ## Sources covering this story - https://developer.nvidia.com/blog/five-ways-nvidia-co-design-maximizes-the-value-of-every-byte-in-the-ai-factory/ — --- _Summary written by Brifing from the original reporting. Copyright in the original article belongs to its publisher; read the full piece at the link above._