The Flaws and Limitations of RISC-V Design
Performance issues and design flaws of RISC-V architecture in embedded systems.
1RISC-V's Universal Compatibility Claim
RISC-V advocates claim the architecture can be effective in both supercomputers and small embedded systems. However, the needs of high-performance CPUs and low-cost microcontrollers are fundamentally contradictory. Design choices affect not only microarchitecture but directly impact CPU architecture. For instance, RISC-V has potential in ultra-cheap single-use microcontrollers, but this is despite its ISA design rather than because of it, merely being an improvement over archaic architectures like 8051.
2Core Needs in Embedded Systems
Cheap microcontroller cores are typically used to manage hardware blocks. In devices like MP3 players, SD cards, or USB drives, the main work is done by custom IPs while the CPU only occasionally updates registers. The critical factors here are interrupt latency (lower is better) and size (smaller is better). Hardware multipliers or dividers are unnecessary, and privilege separation isn't required since no untrusted external code is executed.
3Interrupt Latency Comparison
RISC-V's RV32IC or RV32EC versions are incomplete without the Zicsr extension for interrupt handling. Without Zicsr, interrupt handlers lack a proper way to temporarily store registers. For example, an interrupt handler meeting ABI requirements needs at least 21 cycles. Exiting adds another 20 cycles. With JAL and RET instructions, the total interrupt cost reaches 44 cycles. Competitor Cortex-M0 completes interrupt entry in 15 cycles and exit in 12, totaling just 27 cycles—far more efficient.
4RV32E's Limited Advantage
RV32E halves the number of registers, reducing interrupt handling cost to 38 cycles. Yet this still lags behind Cortex-M0's 27 cycles. RISC-V's base ISA forces vendors to develop non-standard solutions. CLIC and other proprietary 'fast IRQ' extensions attempt to mask RISC-V's fundamental design flaws, further fragmenting the so-called 'standard.'
5Problems with Compressed Instructions
RISC-V's compressed instruction set (C extension) has critical design flaws. For example, a 16-bit instruction storing a byte to register-plus-offset supports only 0–3 offset values. Halfword storage allows just 0 or 2 offsets. Word storage is relatively better (0–124 bytes), but other instructions' limited ranges reduce overall efficiency.
6Performance and Code Density
Code density is vital in embedded systems for ROM/RAM space savings. RISC-V's compressed instructions fail to deliver expected savings in some scenarios. Notably, interrupt handler prologues are larger and slower than Cortex-M0's hardware-supported zero-byte path, questioning RISC-V's practicality in embedded systems.
7Risk of Architectural Fragmentation
RISC-V's base ISA shortcomings push vendors to create proprietary extensions. This risks incompatible solutions across vendors, fragmenting the ecosystem. For instance, one vendor's 'fast IRQ' extension might not work with another's, harming software portability and maintenance costs.
8Direct Comparison with Cortex-M0
Cortex-M0 is RISC-V's primary competitor in embedded systems. Hardware-assisted register stacking cuts interrupt handling cost by 40% compared to RISC-V. Its Thumb compressed instruction set also offers wider offset ranges, improving code density. For RISC-V to lead, it must rethink its core design.
9Historical Context: 8051 and Beyond
RISC-V's potential success in cheap microcontrollers hinges on replacing archaic architectures like 8051. But 8051's low-performance bar sets an easy target. Real competition lies with modern architectures like ARM Cortex-M. For RISC-V to compete, it must rapidly evolve its hardware and software ecosystem.
10Vendors' Proprietary Solutions
RISC-V's slow base interrupt mechanism drives vendors to develop extensions like CLIC. However, these non-standard solutions risk compatibility issues across chips. For example, one vendor's auto-stacking might not work with another's software, undermining RISC-V's 'open standard' claim.
11Software Development Challenges
RISC-V requires interrupt handlers to be written in assembly due to lacking hardware register stacking. This complicates development and increases error risk. Competitors like Cortex-M0 allow writing handlers directly in C, offering significant ease to developers.
12Conclusion: RISC-V's Future
RISC-V shows promise, especially in low-cost embedded systems, but its core design flaws currently leave it trailing leaders. Issues like interrupt latency, code density, and architectural fragmentation could hinder adoption. Vendor extensions offer short-term fixes but threaten ecosystem integrity long-term. RISC-V's success depends on addressing these problems fundamentally.
Original article: Hacker News (news.ycombinator.com) — RISC-V Tasarımının Eksikleri ve Sınırlamaları