# PyTorch Conference 2026: Hardware Acceleration & Compute Infrastructure Deep Dive Exploring cutting-edge kernel engineering and compiler innovations for AI workloads - **Source:** [PyTorch Blog](https://pytorch.org/blog) - **Published:** 2026-09-04 - **Topic:** [Data & AI](https://brifing.si/c/data-ai) - **Original article:** - **On Brifing:** https://brifing.si/s/775a1d09-52b1-4591-a02e-ed75207e9ac8 ## Conference Overview The PyTorch Conference North America 2026 in San Jose (October 20-21) focuses on optimizing PyTorch performance across diverse hardware including GPUs, TPUs, NPUs, and custom ASICs. Over two days, sessions will cover kernel engineering, compiler backends, new accelerators from major vendors, and essential profiling tools. This event brings together leading experts from Amazon, Google, Meta, NVIDIA, AMD, and Intel to share breakthroughs in hardware acceleration. ## Keynote Highlights Amazon's Maen Suleiman will demonstrate how PyTorch now runs natively on Trainium chips without code changes. Google Cloud's Bill Jia presents TorchTPU in production environments with autonomous performance optimization. Core Automation's Mark Saroufim will discuss why linear algebra kernels remain critical bottlenecks and how AI tools are accelerating their development. These keynotes set the stage for deep technical discussions about the future of AI hardware acceleration. ## AMD's MLIR Breakthrough AMD introduces FlyDSL, an MLIR-based GPU kernel DSL integrated into TorchInductor's GEMM compilation pipeline. Liz Li's presentation includes performance comparisons against Triton on AMD Instinct GPUs, showcasing significant improvements in matrix multiplication operations. This represents a major step forward in making AMD hardware more competitive for AI workloads within the PyTorch ecosystem. ## Meta's Heterogeneous Compiler Meta researchers unveil Helion, featuring two new compiler backends: CuteDSL for NVIDIA GPUs and Pallas for TPUs. The system enables single kernel sources to target different hardware architectures, particularly valuable for LLM-agent-written kernels. This innovation addresses growing needs for hardware flexibility in AI model deployment across diverse infrastructure. ## Triton for Beginners Crusoe AI offers an accessible introduction to GPU kernel programming with Triton, teaching developers to build from vector addition to matrix multiplication without requiring CUDA or C++ expertise. This session lowers the barrier to entry for PyTorch developers looking to optimize their models' hardware performance, potentially democratizing access to GPU acceleration techniques. ## NVIDIA's Python-First Approach NVIDIA showcases new Python-first features in CUTLASS, including CuTe DSL extensions and a zero-cost async scheduler. Michael Goldfarb and Guray Ozen demonstrate how these advancements make advanced GPU kernel construction more accessible to Python-centric PyTorch developers, potentially accelerating innovation in GPU-optimized AI models. ## Performance Prediction Model AMD presents PerfModel, an analytical tool that predicts optimal Triton GEMM configurations for AMD GPUs before JIT compilation. Xiaohu Guo's session reveals how this innovation dramatically reduces the cost of exhaustive autotuning, potentially cutting development time for optimized kernels by significant margins. ## Modular's Mojo Language Stefan Lindall from Modular provides an overview of their Mojo language and hardware abstractions that automatically compile specialized fused kernels across diverse chips. The system demonstrates remarkable flexibility, supporting everything from NVIDIA H100s to TPUs and Trainium processors, potentially simplifying deployment across heterogeneous hardware environments. ## Hugging Face's Kernel Library Hugging Face introduces its Kernels library, enabling developers to easily discover and implement optimized custom kernels. Sayak Paul demonstrates how this innovation delivers 2-5x speedups without requiring CUDA expertise, potentially revolutionizing how the open-source community accesses performance optimizations for transformer models. ## Dynamic Shape Optimization Meta and NVIDIA collaborate on new support for capturing and re-parametrizing CUDA Graphs across dynamic shapes. Elias Ellison and Daniel Galvez's presentation shows how this reduces whole-model rewrites and cuts cold-start times for inference serving, addressing a critical pain point in production AI deployments. ## Intel's Triton Strategies Intel engineers present specialized Triton kernel approaches that outperform SYCL on Intel Arc GPUs for vLLM's inference paths. Whitney Tsang and Artur Fierka demonstrate unified attention and fused MoE techniques that could make Intel hardware more competitive in the AI inference market. ## Industry Implications The conference highlights how hardware diversity is driving innovation in compiler technologies and kernel optimization. As AI models grow more complex and hardware ecosystems more fragmented, these advancements in portable performance optimization become increasingly critical for maintaining PyTorch's position as the leading framework for AI research and production. ## Sources covering this story - https://pytorch.org/blog/your-guide-to-hardware-acceleration-compute-infrastructure-at-pytorch-conference-north-america-2026/ — --- _Summary written by Brifing from the original reporting. Copyright in the original article belongs to its publisher; read the full piece at the link above._