# Nvidia Quietly Lowers Bandwidth Targets for Vera Rubin Hardware Revised specifications reveal significant reductions in HBM4 memory and NVLink interconnect performance. - **Source:** [Latest from TechRadar](https://www.techradar.com/feeds.xml) - **Published:** 2026-10-31 - **Topic:** [Software & Engineering](https://brifing.si/c/engineering) - **Original article:** - **On Brifing:** https://brifing.si/s/8ff4a34c-5b77-4e94-8376-8aabe2cbdde1 ## Silent Specification Downgrade Nvidia recently lowered the published HBM4 bandwidth for its Vera Rubin GPUs from 22 TB/s to 19.2 TB/s. Additionally, NVLink 6 bandwidth was reduced from 3.6 TB/s to 3 TB/s per GPU. These changes occurred quietly between September 1 and September 11, 2026, without any official press release or public explanation. ## Impact on Rack Configurations The HGX Rubin NVL8 board experienced the most significant performance hit, losing 26% of its memory bandwidth and dropping from 2.3 TB to 2 TB of HBM4 capacity. Aggregate rack-scale memory bandwidth also slipped from 1,580 TB/s to 1,400 TB/s, while the two-GPU Vera Rubin Superchip fell from 44 TB/s to 38.5 TB/s. ## Timing and Production Reality These revisions appeared shortly after Nvidia’s second-quarter results confirmed that Rubin racks were already operating at major cloud providers like Google Cloud and Microsoft Azure. Because these systems are currently reaching customers, the updated figures likely represent the actual hardware performance rather than a future target, reflecting the current state of production shipments. ## Supply Chain and JEDEC Standards The JEDEC HBM4 standard, published in April 2025, specifies 2 TB/s per stack at 8 Gb/s per pin. Nvidia’s ambitious targets for higher speeds faced development hurdles with suppliers like SK hynix and Samsung. These revisions suggest that prioritizing delivery schedules over chasing elusive, higher-bandwidth goals became the necessary strategy for the company. ## Competitive Landscape Shifts On paper, AMD’s Instinct MI455X now leads in per-GPU memory bandwidth. By utilizing wider interfaces rather than pushing for extreme pin speeds, AMD avoided the technical bottlenecks Nvidia encountered. Against the revised 1,400 TB/s aggregate bandwidth for Rubin, AMD’s Helios platform now holds a roughly 19% lead in total system memory bandwidth. ## Inference and Performance Metrics While raw bandwidth figures have decreased, the Rubin architecture remains significantly faster than the previous Blackwell generation, offering 2.4 times the bandwidth of an 8 TB/s Blackwell GPU. However, the original claim of a 2.8x improvement remains on Nvidia’s blog, creating a discrepancy between current marketing materials and the updated technical specifications. ## Unresolved Technical Discrepancies Current documentation contains internal inconsistencies, as some per-GPU tables still advertise the original 22 TB/s figure while system totals reflect the lower, revised values. Nvidia has not clarified whether these lower figures result from disabling HBM4 stacks or running the memory at lower speeds, leaving the exact hardware configuration details currently unconfirmed. ## Strategic Implications for Customers For professional users focused on inference, bandwidth is a critical bottleneck. Although Nvidia maintains that kernel efficiency is more important than peak specs, the reduction in bandwidth could impact token generation costs. Customers should monitor whether the promised 10x efficiency gains over the GB200 NVL72 remain valid under these new, lower performance constraints. ## Sources covering this story - https://www.techradar.com/pro/nvidia-forced-to-dial-back-key-bandwidth-targets-on-vera-rubin-hardware-tweaks-will-affect-target-specifications-for-memory-and-interconnect-fabric — --- _Summary written by Brifing from the original reporting. Copyright in the original article belongs to its publisher; read the full piece at the link above._