# A Deep Dive into AMD's New MI400 Series Data Center Accelerators Technical details of AMD's next-gen GFX1250 accelerators revealed through LLVM commits. - **Source:** [Hacker News: Front Page](https://brifing.si/source/b07aa772-b1a0-4a76-aa18-719c6f9e2dde) - **Published:** 2026-07-19 - **Topic:** [Data & AI](https://brifing.si/c/data-ai) - **Original article:** - **On Brifing:** https://brifing.si/s/99cd838a-53b3-4cf9-82bf-29d7aa261fe5 ## The Arrival of Next-Gen Accelerators AMD is preparing to launch its MI400 series of data center accelerators. Two new chips codenamed GFX1250 and GFX1251 are specifically designed for machine learning and high-performance computing. Insights from LLVM commits provide significant clues about this new hardware generation. ## Machine Learning Focused GFX1250 GFX1250, branded as MI455X, is an accelerator chip targeting the machine learning market. Designed to power Helios rack systems, it features architectural improvements over previous CDNA accelerators, specifically optimized for AI workloads. ## Architectural Innovations GFX1250 introduces the WGP (Workgroup Processor) architecture. Each WGP consists of two pairs of SIMD32 arrays. Unlike previous generations, it now features a shared vector L0 cache for the entire WGP, making CU distinction unnecessary for compilers. ## Wave32 Mode and Performance GFX1250 operates exclusively in Wave32 mode, lacking RDNA's Wave64 support. Its ability to run 20 waves per SIMD (four more than RDNA4) addresses high register pressure in machine learning workloads, offering significant performance potential. ## Register and Cache Management GFX1250 allows each wave to access up to 1024 VGPRs (Vector General Purpose Registers), nearly doubling CDNA's 512-register limit. The 320kB LDS (Local Data Share) capacity offers twice CDNA4's performance, enhancing data-intensive operations. ## WGP Cache Innovation A major GFX125X innovation merges LDS and vector L0 caches into WGP Cache. This flexible 448KB structure can be partitioned based on programmer needs, following NVIDIA and Intel's approach to improve efficiency in data center applications. ## Compute Capabilities GFX1250 supports packed fp32 operations inherited from CDNA2, enabling two fp32 operations per SIMD lane simultaneously. Combined with more powerful SDMA units from CDNA, these features promise significant performance gains for machine learning workloads. ## Purged Graphics Features The GFX125x series is designed as a purer compute accelerator than even CDNA architectures, with all graphics features (texture processing, ray tracing etc.) removed. This optimization makes perfect sense for data-center-focused use cases. ## WMMA Support GFX1250 features WMMA (Wave Matrix Multiply-Accumulate) support introduced in RDNA4. Replacing older MFMA (Matrix Fused Multiply-Add), WMMA forms the foundation of machine learning capabilities, offering more efficient matrix operations. ## Missing Dynamic VGPR Surprisingly, GFX1250 lacks RDNA4's dynamic VGPR allocation feature, despite its importance for high-register-pressure ML workloads. However, the 1024 VGPR support appears sufficient to compensate for this omission in most scenarios. ## Competitive Comparison Compared to NVIDIA's Blackwell and Intel's accelerators, GFX1250 shows distinct differences. AMD's solution offers a purer compute-focused design while competitors retain some graphics features. Register and cache improvements may give AMD a competitive edge in specific workloads. ## The Future of Data Centers AMD's GFX1250 architecture promises a significant leap for AI and machine learning workloads. WGP Cache, expansive register files, and compute-focused design may set new performance standards in data centers, strengthening AMD's position in the AI accelerator market. ## Sources covering this story - https://chipsandcheese.com/p/scrying-the-amd-gfx1250-llvm-tea — --- _Summary written by Brifing from the original reporting. Copyright in the original article belongs to its publisher; read the full piece at the link above._