Commodore 64 Hardware Simulator: Pin-Level Motherboard Analysis
A cycle-accurate simulator for testing physical hardware faults on the C64 motherboard.
1Pin-Level Hardware Simulation
The c64-hw-sim project provides a cycle-accurate simulation of the Commodore 64 motherboard, specifically the ASSY 250407 model. Unlike traditional emulators, this tool models the board netlist pin by pin. Users can physically manipulate components by lifting chip legs, shorting pins to ground, or removing chips to observe real-time electrical consequences.
2Emergent Fault Behavior
The simulator does not rely on pre-programmed error states or visual hacks to represent broken hardware. Instead, it computes screen output and system behavior directly from the circuit state. When a component is removed or faulted, the resulting screen artifacts are the direct mathematical consequence of the underlying electrical signal changes.
3Performance and Hardware Constraints
Due to the high computational overhead of simulating every individual pin, the software does not run at real-time speeds. On an Apple M5 Max, it achieves 48% of real-time speed, while an Apple M3 Max reaches 31%. It is designed for diagnostic analysis rather than gaming or standard software execution.
4Diagnostic Visualization Tools
The interface includes a virtual oscilloscope and logic probe to monitor signal states across the board. Pins are color-coded to indicate status: red for high, blue for low, yellow for pulsing, and gray for floating. Magenta highlights occur when two outputs conflict, providing clear visual feedback on complex electrical contention issues.
5Integration and Component Sources
The project leverages existing high-quality open-source components for its core functionality. It uses Andre Weissflog's cycle-accurate chip cores for the 6502, VIC-II, and SID, while the board layout is derived from bwack's KiCad replica. PLA equations are sourced from Mark Smith and Marko Mäkelä’s previous read-out efforts.
6Automated Fault Testing
Developers can execute headless tests using the --headless flag to simulate specific hardware failures. The tool supports automated scripts, such as tests/faults.sh, which runs 31 common hardware faults. This allows for systematic verification of expected symptoms against the simulated output, facilitating a deeper understanding of how specific pin failures affect system operation.
7Electrical Signal Modeling
The simulator implements a drive-strength model where the strongest signal wins on any given net. Floating lines are modeled with drift and noise, allowing for erratic behavior similar to real MOS inputs. While thresholds and crosstalk values are estimates, they provide a functional approximation of how physical hardware reacts to open circuits.
8Scope and Future Development
Current simulation covers the logic, RAM, and ROM components, but excludes analog sections like the video output, SID filters, and power supply. Future updates are planned to include internal chip faults, such as bad DRAM cells, and bridges between nets, further expanding the utility of this tool for hardware debugging and research.