NVIDIA CUDA 13.5 Launches with Vera Rubin GPU Architecture Support
New toolkit release enhances multi-GPU communication, resource partitioning, and Python-based development workflows.
1Vera Rubin Architecture Support
NVIDIA CUDA 13.5 has reached general availability, marking a significant milestone for the Vera Rubin GPU architecture. This release transitions support from early developer access to production-ready status. Furthermore, Windows on Arm support is now extended to the NVIDIA DGX Station for Windows, broadening the platform's accessibility for enterprise-grade accelerated computing tasks.
2Locality Domain Enhancements
The update introduces advanced streaming multiprocessor (SM) partitioning options. Applications can now choose between uniform partitions or configurations that include all available SMs using the cudaDevSmResourceSplit API. This flexibility allows developers to optimize hardware utilization based on specific workload requirements, balancing the need for predictable performance against maximum raw compute capacity.
3MPS v3 Resource Management
NVIDIA Multi-Process Service (MPS) v3 introduces weighted timeslicing and sophisticated load balancing. Workloads can now borrow or lend SM capacity dynamically, while cgroup-based routing simplifies resource policy enforcement. These features allow for more granular control over how multiple clients share GPU resources, ensuring stable performance even during complex, multi-tenant execution scenarios.
4Advanced Memory Accounting
MPS v3 includes a new polling-based fallback for memory accounting, designed to function when cgroup threshold notifications are unreliable. By reading usage limits directly, the system ensures accurate eviction decisions. Developers can force this behavior via the nvidia-cuda-mps-control interface, removing dependence on external notification delivery for critical memory management tasks.
5CUDA Graph and Batching
CUDA 13.5 enhances CUDA Graph support by enabling batched 1D memory copies within stream captures. Applications can now include existing copy calls without modifying syntax, allowing for more efficient reusable graph workflows. Additionally, developers can update compatible copy addresses and sizes directly, simplifying the management of dynamic data pipelines in production environments.
6Driver Model Transitions
With the introduction of the Rubin architecture, NVIDIA has shifted driver support requirements. The Tesla Compute Cluster (TCC) mode is no longer supported on Rubin or later GPUs. Developers must transition to the Windows Driver Display Model (WDDM) or the compute-only Microsoft Compute Driver Model (MCDM) to ensure continued system compatibility.
7Multi-GPU Communication
CUDA Tile kernels now support direct multi-GPU communication via NVLink and NVSwitch fabrics. Using unicast and multicast pointers, kernels can perform cross-GPU reductions and stores. This capability enables advanced workloads like fused matrix multiplication, allowing developers to combine communication and computation directly within the kernel for improved latency and throughput performance.
8SIMT Interoperability Preview
A new public preview allows CUDA Tile kernels to call device functions from SIMT libraries directly. This integration supports libraries such as NVSHMEM, CCCL Coop, and MathDx. By eliminating the need to pass data through global memory between kernel boundaries, this feature significantly streamlines the execution of complex mathematical operations within tile-based code.
9CUDA Python 1.2 Updates
The CUDA Python core library 1.2 introduces batched memory copies via copy_batch and Programmatic Dependent Launch (PDL). These features allow Python applications to overlap kernel execution within the same stream. Furthermore, more flexible CUDA Graph updates enable developers to modify kernel parameters and memory copies without the overhead of full graph reinstantiation.
10CCCL 3.5 Library Additions
CCCL 3.5 brings public tuning APIs for CUB, allowing developers to customize parameters like threads per block and vectorization. The release also includes reproducible floating-point scans and a new batched Top-K selection algorithm. These tools are integrated into FlashInfer, specifically designed to optimize token selection processes within large language model inference pipelines.
11Developer Tuning Policies
Developers can now attach custom tuning policies to the execution environment using the cuda::execution::tune API. This allows for specific optimizations based on GPU compute capability, such as adjusting items per thread or load modifiers. These policies provide a standardized way to ensure optimal algorithm performance across diverse hardware configurations and workloads.
12Strategic Impact of Release
CUDA 13.5 represents a major step in scaling accelerated computing for AI and enterprise workloads. By providing deeper control over hardware resources, communication fabrics, and library interoperability, NVIDIA enables developers to push performance boundaries. This release establishes the foundational software environment required to fully leverage the capabilities of the Vera Rubin architecture.